Lattice Releases World's Fastest and Smallest PLD

Industry's First Low Power, 1.8-volt ISP(TM) Simple PLD -- Available in Space-Saving 32-Pin QFN Package

The ispGAL22V10A family of devices couples industry-leading performance of up to 455MHz operating frequencies (fMAX), 2.3ns pin-to-pin delays (tPD) and low standby power (less than 300micronW) while supporting I/O standards of 3.3, 2.5 and 1.8 volts. The ispGAL22V10A family is offered in a new 32-pin QFN (Quad Flat-pack No-lead) package along with a traditional 28-pin plastic leaded chip carrier (PLCC) version. The 32-pin QFN is 84% smaller (5mm x 5mm) than traditional PLCC packaging, making it ideal for high-density PCBs used in small-scale consumer and portable electronic applications such as cellular phones, pagers and PDAs.

The ispGAL22V10AC is the industry's first 1.8-volt in-system programmable SPLD. The ispGAL22V10A family is also offered in 2.5 and 3.3-volt power supply versions, designated as the ispGAL22V10AB and ispGAL22V10AV, respectively. The ispGAL22V10A family provides enhanced I/O support including LVCMOS 3.3V, 2.5V and 1.8V. For devices in the QFN package, output voltage is independent of core supply voltage through the use of a separate Vcco connection. The I/Os on the ispGAL22V10A family are 5-volt tolerant and can be "hot socketed" to facilitate connection to legacy chips and interfaces.

"With our E2CMOS(R) low-power cell and advanced CMOS design techniques, the ispGAL22V10A family offers the highest performance, while simultaneously delivering low standby power," said Steve Stark, Lattice Semiconductor's director of product marketing.

Ultra-High Performance

In the 32-pin QFN package, the ispGAL22V10A provides 2.3ns pin-to-pin delay (tPD), 2.0ns clock-to-output delay (tCO), 1.3ns set-up time (tSU) and 455MHz operating frequencies (fMAX). Lattice's previous generation of 3.3V GAL(R)22LV10s were, until now, the fastest low voltage 22V10s in the market at 4ns tPD. The new ispGAL22V10A family at 2.3ns is 43% faster than the earlier GAL22LV10 and 77% faster than available competitive devices.

Space-Saving QFN Package

The ispGAL22V10A family is offered in a new space-saving 32-pin QFN (Quad Flat-pack No-lead) package, a technology based on chip scale packaging. The 32-pin QFN is 84% smaller (5mm x 5mm), 80% thinner (0.9mm) and 95% lighter (0.06 grams) than the 28-pin PLCC package.

Software Support

The ispGAL22V10A family is supported by Lattice's new software platform ispLEVER(TM) Version 3.0 Service Pack 2003.01. Programming support will be through Lattice's ispVM(R) version 13.0 software, which is downloadable from the Lattice web site.

Price and Availability

The ispGAL22V10A family of devices is available now in the 28-pin PLCC package as well as the space saving 32-pin QFN package. Pricing, in high volumes of 50,000 pieces or more, will be less than $1.00.

About Lattice Semiconductor

Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of high-performance ISP programmable logic devices (PLDs), Field Programmable Gate Arrays (FPGAs) and Field Programmable System-on-a-Chip (FPSC) devices. Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503/268-8000, FAX 503/268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, L (& design), Lattice (& design), E2CMOS, GAL, in-system programmable, ISP, ispGAL, ispLEVER, ispVM and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

NOTE TO EDITORS: Throughout the release the following should appear with subscript characters: fmax (max is subscript), tpd (pd is subscript), tco (co is subscript), tsu (su is subscript).

CONTACT: Lattice Semiconductor Corporation
             Sean Hildenbrand, 503/268-8680
             Sean.hildenbrand@latticesemi.com